Low noise amplifier

ABSTRACT

An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor (Q 1 ); a second transistor (Q 2 ); and a third transistor (Q 3 ), wherein: the first (Q 1 ), second (Q 2 ) and third (Q 3 ) transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.

TECHNICAL FIELD

This invention relates to a low noise amplifier, particularly for use in mm-wave applications, a method of operating the amplifier and a receiver incorporating the amplifier.

BACKGROUND ART

Recent Federal Communications Commission (FCC) regulations has freed up some unlicensed millimeter-wave (mm-wave) frequencies [1]-[2]. Such regulations stem from lower overcrowded spectrums and the increasing demand of users for high data rate wireless communications and radar sensors. Receivers targeting microwave and mm-wave applications based on the wireless metropolitan area network standards ranging from 10-66 GHz, ultra-wideband radar vehicular sensor from 22-29 GHz, and military radar for unmanned aerial vehicle (UAV) from 35-37 GHz [3], etc. are essential to achieve the user end demands. This frequency spectrum allocation still encounters adjacent channel coexistence, similar to lower frequency spectrums, like radio astronomy at 23.6-24 GHz, industrial-scientific-medical (ISM) at 24.05-24.25 GHz, local multipoint-distribution system (LMDS) at 31 GHz, and cloud radar at 35 GHz [4]. In fact, it presents a dilemma for some sensitive frequency bands where overlapping exists. The design of silicon-based radio frequency integrated circuit (RFIC) receiver front ends at these frequencies for wideband performance with simultaneously high gain and high linearity is very challenging.

Low-noise amplifier (LNA) plays a crucial role in achieving high gain and linearity over wide operating frequency ranges for these receivers. Active balun-LNAs are LNAs capable of providing differential outputs from a single-ended input and are important component in receivers. Various wideband active balun-LNAs on silicon at low frequencies, which implement active and passive feedback mechanisms to improve linearity, gain and phase errors mismatches, have been reported [5],[6]. However, employing active feedback comes at the expense of power and nonlinearity rendering the harmonics cancellation ineffective [6]. A linearization technique based on derivative superposition and its improved derivative version tend to provide impressive input referred third order intercept point (IIP₃) [18], [20]. The derivative superposition methods use auxiliary N/PMOS path in weak inversion to cancel the third-order nonlinear current of the main transconductance gain-stage path, thus enhancing IIP₃. Nonetheless, this improvement is subject to deter the second inter-modulation product (IP₂) due to nonlinear cross terms between the two paths [18]. Further, current-mode balun-LNA based common-gate common-source structures with bias control and output conductance kept constant show optimum behavior for both noise and linearity [14], [19]. Such constrain across wideband is costly in terms of power consumption and subject to process, voltage, and temperature variations. Another approach is making third inter-modulation IM3 cancellation independent of frequency in bipolar junction transistor (BJT) [15]-[17]. A second-harmonic control with fully differential mode configuration using BJT devices facilitates frequency independent IM3 cancellation [15]. In [16]-[17], IM3 cancellation happens due to current hyperbolic tangent behavior from dual gated BJT devices in differential and pseudo-differential modes added to the output. However, the cost is doubled in noise and power consumption.

All of these techniques were implemented in designs operating below 2.4 GHz. A 20 GHz balun-LNA using 0.25 μm SiGe BiCMOS technology was reported in [7]. This balun-LNA [7] consists of a common-emitter gain stage followed by a single-to-differential output buffer stage using a common-emitter common-base (CE-CB) structure with ac current source. This design suffers from very high phase and gain mismatches, thus limiting the bandwidth. These works show a tradeoff between linearity, power consumption, and gain.

SUMMARY OF INVENTION

Aspects of the invention are recited in the accompanying claims.

One aspect of the invention provides an amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor; a second transistor; and a third transistor, wherein: the first, second and third transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement.

Preferably, the transconductance cell is configured with the collector terminal of the first transistor coupled to the base terminal of the second transistor and the emitter terminal of the third transistor.

Conveniently, the amplifier further comprises: a first inductor coupled to the emitter of the first transistor; a second inductor coupled between the collector of the first transistor and the base of the second transistor, wherein the first inductor and the second inductor are arranged to operate respectively as a first coil of a transformer and a second coil of a transformer.

Advantageously, the transformer is configured to perform at least one of increasing the voltage gain of the amplifier and/or increasing the signal bandwidth of the amplifier.

Preferably, the signal input arrangement comprises an impedance matching circuit which is coupled to the first transistor, the impedance matching circuit comprising the first inductor and a third inductor each coupled to the base of the first transistor.

Conveniently, the amplifier further comprises a fourth inductor coupled between the emitter of the third transistor and the collector of the first transistor.

Advantageously, the collector of the second transistor is coupled to the emitter of a fourth transistor, and wherein the first, second, third and fourth transistors are arranged in a common-emitter configuration.

Preferably, the base of the third transistor, the base of the fourth transistor and a power supply input are coupled to one another.

Conveniently, the signal output arrangement comprises: a first output portion coupled to the collector of the third transistor; and a second output portion coupled to collector of the fourth transistor.

Advantageously, the first output portion includes a first pair of series connected inductors and a first output terminal coupled to the connection between the first pair of inductors, and wherein the second output portion includes a second pair of series connected inductors and a second output terminal coupled to the connection between the second pair of inductors.

Preferably, the amplifier further comprises: a first resistor coupled between the first output portion and the power supply input; and a second resistor coupled between the second output portion and the power supply input.

Conveniently, the inductance of the first pair of inductors is equal to the inductance of the second pair of inductors.

Advantageously, the amplifier is configured to be operable with a passive mixer and a trans-impedance amplifier and the signal output arrangement is coupled to a class AB amplifier.

Preferably, the first signal comprises at least one signal having a frequency of 22 GHz to 35 GHz.

Conveniently, the amplifier is constructed using a SiGe BiCMOS process.

The present invention provides an improved low noise amplifier with wideband characteristics, high linearity and low power consumption.

Embodiments of the invention incorporate some or all of the following features either individually or in any combination: a low-power-consumption wideband 0.18 μm BiCMOS active balun-LNA with linearity improvement technique for millimeter-wave applications is proposed. The linearity technique utilizes constant Gm transconductance structure with second-order intermodulation (IM₂) cancellation that provides robustness to input and output variations. The constant Gm is established with equal emitters' area ratios and proper base-emitter biasing voltage; thus improving linearity. Furthermore, power saving is achieved using inductive coupling boosting the overall Gm structure and reducing the current consumption for the auxiliary gain stage. The measured balun-LNA's power gain between the input and two outputs are 15.4 dB and 15.6 dB with input return loss greater than 8.7 dB, The gain and phase mismatches are less than 1.8 dB and 12°, respectively. The balun-LNA noise figures between the input and two outputs are less than 5.8 dB and 7.09 dB at 35 GHz. The measured P1dB's and IIP3's are more than −14.8 and −6 dBm across 22-35 GHz, respectively, and the total power consumption is less than 9 mW drawn from 1.8V power supply.

One embodiment of the low noise amplifier is a 0:18 μm SiGe BiCMOS 22-35 GHz active balun-LNA with high linearity and low power consumption.

The linearity improvement is attained using a new linearity technique based on a constant Gm-cell transconductance that forms the balun-LNA structure of the embodiment.

The constant Gm-cell transconductance is established through equal emitters' area ratios of the balun-LNA embodiment. The constant small-signal Gm-cell transconductance remains independent of input and output variations under large-signal behavior and provides second-order intermodulation (IM₂) cancellation, resulting in improved linearity.

The low power consumption is due in part to the coupled inductors used between cascaded stages. The balun-LNA embodiment targets multi-standard multi-channel receivers' applications ranging from 22-35 GHz that require high linearity. Many microwave and mm-wave applications not only coexist, but also overlap each other on the same frequency spectrum, making the linearity the bottle neck for the receiver's dynamic range.

BRIEF DESCRIPTION OF DRAWINGS

In order that the present invention may be more readily understood, reference is made by way of example to the following drawings, in which:

FIG. 1. shows a schematic of a low noise amplifier in a balun-LNA.

FIG. 2. shows the small signal model of the balun-LNA's input impedance.

FIG. 3. shows a comparison of magnitudes of Z′_(B) with and without transformer.

FIG. 4. shows the linearity model analysis for the conventional common-emitter gm stage as well the balun-LNA embodiment Gm structure including the effect of the transformer.

FIG. 5. shows comparison curves for (a) Cascode LNA, (b) balun-LNA with transformer, (c) balun-LNA without transformer.

FIG. 6. shows the noise source model of the balun-LNA embodiment.

FIG. 7. shows NF values for the differential output of the balun-LNA embodiment with ideal coupling coefficient; K; and transformer multiple turns n.

FIG. 8. shows a stacked transformer layout structure and its schematic.

FIG. 9. shows inductance values; L_(e1), L_(b2), and coupling coefficient K, for stacked transformer using IE3D.

FIG. 10. shows a die photograph of the balun-LNA embodiment.

FIG. 11 shows the measured and simulated input return losses (S₁₁) for the balun-LNA.

FIG. 12 shows the measured and simulated output return losses S₂₂ and S₃₃.

FIG. 13 shows S₂₁ and S₃₁ with a gain of 15.6 dB and 15.4 dB.

FIG. 14 shows the measured stability of the balun-LNA embodiment in terms of the stability parameter p, derived from the measured S-parameters.

FIG. 15 shows the measured noise figures for both channels.

FIG. 16 shows the measured gain and phase imbalances.

FIG. 17 shows the measurements of the 1-dB power compression points (P1dB₂₁ P1dB₃₁) and the input referred third order intercept points (IIP3₂₁ and IIP3₃₁) for both channels for the frequency range of 22-35 GHz.

FIG. 18 shows a receiver chain for microwave and mm-wave coexistent applications 22-44 GHz.

DETAILED DESCRIPTION

FIG. 1 shows a schematic of an embodiment of a 22-35 GHz (single-to-differential) wideband active balun and Low Noise Amplifier (LNA) with high gain, high linearity, and low power consumption.

Embodiments of the invention are described in detail below in relation to specific figures. The features disclosed in this description in relation to a specific embodiment or in relation to a specific figure are not restricted to adoption in only that embodiment or in only that figure. Such features described in relation to a particular embodiment or in relation to a specific figure may also be adopted in other embodiments or in connection with other figures unless there is a specific technical conflict between the embodiments or figures. Accordingly, the features recited in the description are embodied in the invention, as appropriate, either separately in relation to a particular embodiment or in relation to a specific figure, or in any combination of such features.

The balun-LNA embodiment architecture of FIG. 1 consists of a main transconductance gm gain stage, Q₁, coupled to an auxiliary gain path, Q₂, through a transformer. The coupled transformer increases the signal swing at the input of the second stage, thus boosting the Gm transconductance, hence gain, and reducing the power consumption. The composite Gm cell defined by transistors Q₁, Q₂, and Q₃ plays a major role in improving the linearization of the structure. The stipulated total Gm stays constant even in the presence of variations in gm₁ of Q₁ and gm₂ of Q₂ due to high input power. As the collector currents of transistors Q₁ and Q₂ vary from their quiescent bias under large voltage swing; the gm's dependency on equal emitters' area (A_(e)) ratios keeps the overall Gm-cell constant. The overall Gm's constant and frequency-independent characteristic behavior with IM2 cancellation results in linearity enhancement.

A simple wideband input matching network is established using inductors L_(b) and L_(e1) similar to [10]. The effect of the coupling transformer (L_(e1), L_(b2)) on the input matching is considered thoroughly in the later in the description. Inductive shunt peaking is used at the output loads (output portions) to extend the matching bandwidth of the balun-LNA.

The noise due to the cascode transistor Q₃ is reduced by adding an inductor L_(m) to resonate away the parasitic capacitance at the emitter, thus reducing the output noise.

Input Matching Network

FIG. 2 shows the small-signal input impedance of the balun-LNA derived from its schematic in FIG. 1. g_(m) is the small signal transconductance of Q₁. R_(eq2) is defined as ω_(T)L_(e2) of Q₂, I_(p) and I_(s) are the primary and secondary currents of the transformer.

To keep the analysis simple; the input impedance of the balun-LNA is split into two sections Z_(B) and Z′_(B), which represent the input impedances looking into the respective networks. Under the perfect matching condition, Z_(B)=Z′*_(B). Z_(B) forms a pi-network with wideband matching characteristics, whose quality factor (Q) reduces due to the loading of the network represented by Z′_(B). For the ac coupled transformer (L_(e1) and L_(b2)) in Z′_(B), the coupling coefficient K and the number of turn n can cause the optimum matching point to shift; yet keeping wideband impedance matched to the input port. To study this effect, an expression for the complex conjugate impedance Z′*_(B) is derived. Z′*_(B) is found using the small-signal model in FIG. 2 whereas the adapted transformer model is similar to that in [13]. Applying Kirchhoff current law (KCL) at nodes E₁, C₁ and B₂; where M is the mutual inductance;

$K = \frac{M}{\sqrt{L_{P}L_{S}}}$

is the coupling coefficient, and n=√{square root over (L_(P)L_(S))} is the turn ratio of the ac coupled transformer, can lead to Z′*_(B). C_(pad) is defined as the parasitic capacitance due to RF pad on chip. C_(be), C_(be2), and C_(be3) are the parasitic capacitances at the base-emitter junctions of transistors Q₁, Q₂, and Q₃, respectively. Additionally, C_(he), and C_(p2) are the capacitances at the base-collector junction of transistors Q₁ and Q₂. The KCL equations yield, after several manipulations:

$\begin{matrix} {{V_{B}^{\prime}(s)} = {{{i_{B}^{\prime}(s)}\left( {1 + {\frac{1}{{sC}_{be}}\left( {1 + {{sg}_{m}L_{e\; 1}}} \right)}} \right)} - {MsI}_{s}}} & (1) \end{matrix}$

where V′_(B)(s) is the base voltage looking into Z′_(B) network port, and i′_(B)(s) is its current defined as i′_(B)(s)=sC_(be)v_(be).

The secondary current I, of (I) can be derived as

$\begin{matrix} {{I_{s} = {{i_{B}^{\prime}(s)}\left\lbrack \frac{{g_{m}Z_{1}} - {{sM}\left( {{sC}_{be} + g_{m}} \right)}}{{sC}_{be}\left( {Z_{1} - {sL}_{b\; 2} - Z_{2}} \right)} \right\rbrack}}{where}} & (3) \\ {Z_{1} = {{sL}_{m} + \frac{1}{g_{m\; 3} + {sC}_{{be}\; 3}}}} & (4) \\ {Z_{2} = \frac{\left( {\frac{1}{{sC}_{{be}\; 2}} + {sL}_{e\; 2} + R_{{eq}\; 2}} \right)}{1 + {1/{{sC}_{p\; 2}\left( {\frac{1}{{sC}_{{be}\; 2}} + {sL}_{e\; 2} + R_{{eq}\; 2}} \right)}}}} & (5) \end{matrix}$

Substituting I_(S) into V′_(B)(s) and taking the ratio between (1) and (2) gives

$\begin{matrix} {{Z_{B}^{\prime}(s)} = {1 + {\frac{1}{{sC}_{be}}\left\lbrack {1 + {{sL}_{e\; 1}\left( {g_{m} - \frac{{s({Kn})}g_{m}Z_{1}}{Z_{1} - {sL}_{b\; 2} - Z_{2}} + \frac{{s^{2}({Kn})}^{2}{{sL}_{e\; 1}\left( {g_{m} + {sC}_{b\; e}} \right)}}{Z_{1} - {sL}_{b\; 2} - Z_{2}}} \right)}} \right\rbrack}}} & (6) \end{matrix}$

Z′_(B)(s) shows that any changes in the coupling coefficient K or the number of turn ratio n for the coupled transformer can affect the poles and zeros alike; thus causing the matching to shift into higher frequency; yet maintaining the wideband characteristics due to poles-zeros cancellation effect.

FIG. 3 shows the schematic level simulation for the magnitude of Z′_(B)(s) with and without the transformer, It is clear that the wideband matching characteristic is maintained with only small variation less than 2Ω in the worst case.

Low Noise Amplifier Linearity

FIG. 4(a) shows the linearity model analysis for the conventional common-emitter gm stage. Using Taylor series expansion approximation, the output collector current for the CE stage is given by

$\begin{matrix} {i_{C} \cong {{gm}\left\lbrack {\sum\limits_{{q = 1},2,\ldots}^{\infty}{\frac{V_{T}}{q!}\left( \frac{v_{i\; n}}{V_{T}} \right)^{q}}} \right\rbrack}} & (7) \end{matrix}$

where gm=I_(Q1)/V_(T), with I_(Q1) being the quiescent current of Q₁ and V_(T) being the thermal voltage, is the voltage to current conversion also known as the small signal transconductance gm; and v_(in) is the input voltage. From (7), taking the q^(th) order derivatives of gm with respect to v_(in) encompasses all nonlinearities for the CE stage. Assuming v_(in)=V_(α) cos(ωt) and taking the ratio between the second and the fundamental harmonic amplitude in a CE stage gives the second-order harmonic distortion as

$\begin{matrix} {{HD}_{2} = {\frac{1}{4}\left\lbrack \frac{V_{a}}{V_{T}} \right\rbrack}} & (8) \end{matrix}$

The collector currents in the proposed Gm stage for the balun-LN A as shown in FIG. 4(b) can be derived using (7) as

$\begin{matrix} {{{i_{C\; 1} \cong {I_{Q\; 1}\left( {\frac{v_{i\; n}}{V_{T}} + {\frac{1}{2!}\left( \frac{v_{i\; n}}{V_{T}} \right)^{2}} + {\frac{1}{3!}\left( \frac{v_{i\; n}}{V_{T}\;} \right)^{3}} + \ldots}\mspace{14mu} \right)}}i_{C\; 2} \cong {I_{Q\; 2}\left( {\frac{v_{2}\left( {1 + {nK}} \right)}{V_{T}} + {\frac{1}{2!}\left( \frac{v_{2}\left( {1 + {nK}} \right)}{V_{T}} \right)^{2}} + {\frac{1}{3!}\left( \frac{v_{2}\left( {1 + {nK}} \right)}{V_{T}} \right)^{3}} + \ldots}\mspace{14mu} \right)}}{i_{C\; 3} \cong {I_{Q\; 3}\left( {\frac{- v_{2}}{V_{T}} + {\frac{1}{2!}\left( \frac{- v_{2}}{V_{T}} \right)^{2}} + {\frac{1}{3!}\left( \frac{- v_{2}}{V_{T}} \right)^{3}} + \ldots}\mspace{14mu} \right)}}} & (9) \end{matrix}$

Using (9), we find the differential output current i_(Out)=i_(C3)−i_(C2) with respect to the input voltage V_(in) assuming i_(C1)=i_(C3) and using the fact that −v₂/v_(in)=−gm₁/gm₃=−A_(e1)/A_(e3), where A_(e1) and A_(e3) represent the emitter area for Q₁ and Q₃, respectively, as

$\begin{matrix} {i_{Out} = \begin{bmatrix} {{{I_{Q\; 3}\left( \frac{{- \left( {A_{e\; 1}/A_{e\; 3}} \right)}v_{i\; n}}{V_{T}} \right)}\left( {1 + \frac{I_{Q\; 2}\left( {1 + {nK}} \right)}{I_{Q\; 3}}} \right)} +} \\ {{\frac{I_{Q\; 3}}{2}\left( \frac{\left( {A_{e\; 1}/A_{e\; 3}} \right)v_{i\; n}}{V_{T}} \right)^{2}\left( {1 - \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{2}}{I_{Q\; 3}}} \right)} +} \\ {{\frac{I_{Q\; 3}}{6}\left( \frac{{- \left( {A_{e\; 1}/A_{e\; 3}} \right)}v_{i\; n}}{V_{T}} \right)^{3}\left( {1 + \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{3}}{I_{Q\; 3}}} \right)} + \ldots} \end{bmatrix}} & (10) \end{matrix}$

Substituting v_(in)=V_(α) cos(ωt) into (10) results in

$\begin{matrix} {i_{Out} = \begin{bmatrix} \left\lbrack \left( {I_{Q3}\left( \frac{{- \left( {A_{e\; 1}/A_{e\; 3}} \right)}V_{a}}{V_{T}} \right)} \right) \right\rbrack \\ \begin{pmatrix} {\left( {1 + \frac{I_{Q\; 2}\left( {1 + {nK}} \right)}{I_{Q\; 3}}} \right) -} \\ {\frac{1}{8}\left( \frac{\left( {A_{e\; 1}/A_{e\; 3}} \right)V_{a}}{V_{T}} \right)^{2}\left( {1 + \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{3}}{I_{Q\; 3}}} \right)} \end{pmatrix} \\ {{\cos \; \varpi \; t} +} \\ {{\frac{I_{Q3}}{4}\left( \frac{\left( {A_{e\; 1}/A_{e\; 3}} \right)V_{a}}{V_{T}} \right)^{2}\left( {1 + {\cos \; 2\omega \; t}} \right)\left( {1 - \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{2}}{I_{Q\; 3}}} \right)} +} \\ {{\frac{I_{Q3}}{24}\left( \frac{{- \left( {A_{e\; 1}/A_{e\; 3}} \right)}V_{a}}{V_{T}} \right)^{3}\left( {\cos \; 3\; {\omega t}} \right)\left( {1 + \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{3}}{I_{Q\; 3}}} \right)} + \ldots} \end{bmatrix}} & (11) \end{matrix}$

From (11), considering the ratios between the second, and the fundamental amplitude harmonics as well between the third and the fundamental amplitude harmonics for the proposed Gm stage gives HD_(2,Gm) and HD_(1,Gm) respectively, as

$\begin{matrix} {{HD}_{2,{Gm}} = {\left( \frac{\left. {\left( \frac{1}{4} \right)\left( \left( \frac{\left( {A_{e\; 1}/A_{e\; 3}} \right)V_{a}}{V_{T}} \right) \right)\left( {1 - \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{2}}{I_{Q\; 3}}} \right)} \right|}{\begin{matrix} \left( {\left( \frac{1}{8} \right)\left( \frac{\left( {A_{e\; 1}/A_{e\; 3}} \right)V_{a}}{V_{T}} \right)^{2}} \right) \\ {\left( {1 + \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{3}}{I_{Q\; 3}}} \right) - \left( {1 + \frac{I_{Q\; 2}\left( {1 + {nK}} \right)}{I_{Q\; 3}}} \right)} \end{matrix}} \right)}} & (12) \\ {{HD}_{3,{Gm}} = \frac{\frac{1}{24}\left( \frac{\left( {A_{e\; 1}/A_{e\; 3}} \right)V_{a}}{V_{T}} \right)^{2}\left( {1 + \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{3}}{I_{Q\; 3}}} \right)}{\begin{pmatrix} {\left( {1 + \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{\;}}{I_{Q\; 3}}} \right) -} \\ {\frac{1}{8}\left( \frac{\left( {A_{e\; 1}/A_{e\; 3}} \right)V_{a}}{V_{T}} \right)^{2}\left( {1 + \frac{{I_{Q\; 2}\left( {1 + {nK}} \right)}^{3}}{I_{Q\; 3}}} \right)} \end{pmatrix}}} & (13) \end{matrix}$

As can be seen from (12), the cancellation of the nonlinearity tor generated due to HD_(2,Gm) is obtained under the condition I_(Q2)(1+nK)²=I_(Q3) which means

$g_{m\; 2} = \frac{g_{m\; 3}}{\left( {1 + {nK}} \right)^{2}}$

and in turn, V_(BE3)≈V_(BE2) and A_(e2)=A_(e3).

Hence, the overall Gm stays constant even in the presence of variations in gm₁ and gm₂ due to large input voltage signal. As the collector currents differ from their quiescent bias under large input power; the gm's dependency on the emitter area ratios keeps the overall Gm constant. This large signal constant gm characteristic results in linearity improvement. As HD_(3,Gm) from (13) cannot be cancelled, equation (13) dictates the linearity limitation for this proposed architecture. However, there is a clear tradeoff between gain and linearity for this balun-LNA architecture. Keeping the aspect ratios A_(e2)=A_(e3)=A_(e4) and

$g_{m\; 2} = {\frac{g_{m\; 3}}{\left( {1 + {nK}} \right)^{2}} = g_{m\; 4}}$

between Q₂, Q₃ and Q₄ maximize the linearity at the expense of gain due to

$G_{m} = {\left( {g_{m\; 1} + {\left( {\frac{g_{m\; 1}}{g_{m\; 3}} + {nK}} \right)g_{m\; 2}}} \right).}$

Also, the gm₂ transconductance increases due to the transformer's product nK which help boost the gain for less dc current. However, given the transformer inductors' sizes and the limited nK value the linearity degradation is very small as depicted in FIG. 5.

The latter shows the simulation results of the input referred IdB gain compression for a cascode LNA and the proposed balun-LNA with and without transformer. All circuits consume 6.4 mA current from a 1.8V supply and achieve 16-dB power gain. The P1dB for the regular cascade LNA and the proposed balun-LNA with and without transformer are −17.9 dBm, −13.37 dBm and −13.26 dBm, respectively. The linearity improvement of the balun-LNA with transformer as compared to the cascade LNA is better than 4.53 dB.

Noise Analysis

The noise of the proposed balun-LNA is dominated by the input stage including the matching network and its auxiliary path. FIG. 6 shows the circuit's main noise sources for the proposed balun-LNA. The noise sources include base and collector noise currents of Q₁ and Q₂. Noise due to the parasitic base resistances R_(bx) and R_(bx2) of Q₁ and Q₂, respectively, and noise due losses of L_(b), R_(Lb), and coupling transformer L_(e1) and L_(b2), R_(Le1) and R_(Lb2), is considered in the noise model. The noise due to the cascade transistor Q₃ is considerably reduced due to inductor L_(m) rendering the degenerated impedance high at resonance, thus making its noise contribution negligible [10]. Furthermore; noise in the auxiliary path due to cascade transistor Q₄ is neglected due to multi-cascaded transconductance gain stages and, as a result, all cascade transistors are neglected in the following analysis.

The equivalent input-referred noise due to the base and collector current shot noise of Q₁, Q₂, and its base parasitic resistance R_(bx2) are given by the equations (A8)-(A12) discussed later in the description. According to (A8) and (A9), the input referred noises of Q₁ increases proportionally with L_(b) inductor's loss. This is because the signal to noise ratio (SNR) between the input and the emitter-base junction is inversely proportional to L_(b). It is clear that there is a tradeoff between the input matching requirement for power transfer and the noise figure for this balun-LNA embodiment structure. However, equations (A8)-(A9) reflect the effect of the coupling transformer on the emitter impedance Z_(e) of Q₁. A higher Z_(e) helps improve the collector current noise at the expense of lower (SNR) at the emitter-base junction. Similarly, equations (A10-A12) show an increase in the SNR at the base-emitter junction of Q₂ raising the voltage gain through the coupling transformer by (nk) factor. The collector shot noise of Q₂ and its parasitic base resistance noise R_(bx2) are improved by the same factor.

The total input referred voltage noise due to Q₁ and Q₂, v² _(niQ) _(1,2) , normalized to the noise voltage source impedance is given by

$\begin{matrix} {\frac{\overset{\_}{v_{{ni},Q_{\; {1,2}}}^{2}}}{4{kTR}_{S}\Delta \; f} \approx {\frac{\Psi_{1}(\omega)}{g_{m\; 1}} + {\left( {\Psi_{2}(\omega)} \right)g_{m\; 1}} + \frac{\Psi_{3}(\omega)}{\left\lbrack {\frac{g_{m\; 1}}{g_{m\; 3}} + {nK}} \right\rbrack} + {{\left( {\Psi_{4}(\omega)} \right)\left\lbrack {\frac{g_{m\; 1}}{g_{m\; 3}} + {nK}} \right\rbrack}g_{m\; 2}} + \frac{\Psi_{5}(\omega)}{\left\lbrack {\frac{g_{m\; 1}}{g_{m\; 3}} + {nK}} \right\rbrack g_{m\; 2}}}} & (14) \end{matrix}$

ψ₁(ω)−ψ₅(ω) are given by the equations (A13)-(A17). This result shows that the collector current shot noise of Q₁ and Q₂ can be improved by increasing gm₁, gm₂ and transformer's product nK, respectively. However, such improvement comes at the expense of degrading the base current shot noise. Hence, there is an optimum value for gm₁ and gm₂ to minimize the total input-referred noise voltage due to Q₁ and Q₂. Differentiating the first two terms and the last two terms of (14) with respect to gm₁ and gm₂ respectively and equating the resultant expressions to zero, results in gm_(1.opt) and gm_(2.opt,) given by

$\begin{matrix} {g_{{m\; 1},{opt}} = \sqrt[\;]{\frac{\Psi_{1}(\omega)}{\Psi_{2}(\omega)}}} & (15) \\ {g_{{m\; 2},{opt}} = {\sqrt[\;]{\frac{{\Psi 5}(\omega)}{{\Psi 4}(\omega)}}\frac{1}{\left\lbrack {\frac{g_{m\; 1}}{g_{m\; 3}} + {nK}} \right\rbrack}}} & (16) \end{matrix}$

The third term in (14) is due to the parasitic base resistance noise, R_(bx2) is limited by gm_(1,opt), A_(e2) emitter area of transistor Q₂, and the transformer coupling factor (nK). The total input referred noise figure of the proposed balun-LNA structure is given by

$\begin{matrix} {{{NF}_{tot}(\omega)}{\approx {1 + {\frac{R_{L_{b}} + R_{bx}}{R_{S}}\left( {1 + {\omega^{2}C_{pad}R_{S}}} \right)} + {2\sqrt[\;]{{\Psi_{1}(\omega)}{\Psi_{2}(\omega)}}} + \frac{\Psi_{3}(\omega)}{\left\lbrack {\frac{1}{g_{m\; 3}}\sqrt[\;]{\frac{\Psi_{1}(\omega)}{\Psi_{2}(\omega)} + {nk}}} \right\rbrack} + {2\sqrt[\;]{{\Psi_{4}(\omega)}{\Psi_{5}(\omega)}}}}}} & (17) \end{matrix}$

FIG. 7 shows the noise figure simulations for the differential output of the balun-LNA. From (17); it is clear that signal to noise ratio (SNR) degradation between the source generator and the base-emitter junction capacitance is due to matching inductance loss L_(b), R_(Lb), the parasitic base resistance, R_(bx), and pad capacitance, C_(pad) Furthermore, an increase in the turn ratio of the coupling transformer could improve the noise figure.

However, the turn ratio cannot be increased randomly considering the coupling transformer non-idealities [21]. Losses associated with parasitic resistances and capacitances at the base of Q₂ measures quadratically compares to the secondary inductance of the transformer. Hence, the self-resonance frequency of the inductance suffers as well as the magnetic coupling, M, reflecting higher noise. Ultimately, there are practical limits for the voltage gain boosting effect and the optimal turn ratio n; thus achieving the lowest noise figure.

Stability and Power Efficiency

The effects of capacitors C_(bc) and C_(p2) on both channels are reduced due to the cascade structure. The added transistors, Q₃ and Q₄, transform the input impedances of the driving stages from negative impedances into a capacitive one; hence the stability is maintained. The transformer is designed in inverting configuration to provide gain boosting without compromising the balun-LNA stability.

The proposed balun-LNA structure having dual g_(m), output from a single-ended input combines the LNA characteristic with the balun behavior into a single block. The inverting coupling transformer boosts g_(m2) by (nK) factor. This topology has two properties:

-   -   1) it can further boosts the voltage gain at the base-emitter         junction, thus reducing the dc bias point for a specific gain         target which means less dc power consumption, and     -   2) by controlling the coupling coefficient polarity, K, through         proper layout of the stacked transformer, the voltage gain can         be increased (with positive K) or remains the same with         bandwidth extended (for negative K).

Transformer and Inductor Layout

The presence of the parasitic capacitors and resistive losses generated from routing paths in integrated circuits causes lower quality factor in passive components, which could be significant at millimeter-wave frequencies. To accurately account for such effects, all inductors are simulated using electromagnetic (EM) simulator IE3D [22]. Inductors L_(d1), L_(d3), and L_(b) are designed using spiral inductor due to their relatively large inductances. However; a careful consideration is being assigned for the metal width trading off the resistive loss, parasitic coupling to the substrate, quality factor and inductors self-resonance frequencies. To guarantee inductors behaviors at mm-wave frequencies; it is important to achieve the quality factor peak beyond the frequency of interest. To reduce all type of losses the top metal M6 is chosen for all inductors. Furthermore; inductors L_(m), L_(e2), L_(d2), L_(d4), and the coupling transformer L_(ei), L_(b2), are all implemented using microstrip transmission lines.

The stacked coupling transformer is shown in FIG. 8 where L_(e1) and L_(b2) consist of primary and secondary inductors; respectively. The transformer inverting configuration is implemented to form a feed-forward path boosting the transconductance gm₂ input stage. All electromagnetic effects from eddy current substrate loss to frequency dependent metal loss are considered in the design process of the transformer.

In order to reduce the parasitic loss effect at high frequency; the stacked transformer is realized with the top metal layers M6 and M5 which are the thickest and farthest from the substrate, thus reducing losses. The quality factor and self-resonance frequency for both L_(ei) and L_(b2) remain almost identical. A high quality factor (Q) for the transformer inductances is needed to reduce its noise contribution into the balun-LNA structure.

For the optimal magnetic coupling between transformer conductors; the metal width for the microstrip transmission lines forming the transformer are set to the smallest possible (7.5 μm) constrained by the ohmic losses, the dc current, and the quality factor. The narrower the conductor dimensions width the higher the magnetic coupling between the transformer turns. However; increasing the metal width leads to higher parasitic capacitance losses to the substrate.

The coupling coefficient, K, for the stacked transformer is limited by the process technology due to metal thickness and minimum layers spacing as well as the optimal turn's ratio at mm-wave frequency. The benefits and limitations of increasing the turn ratios for the stacked transformer have been previously discussed. Thus, the stacked transformer is designed with 1:1 turn's ratio. L_(e1) and L_(b2) inductances are 82 pH and 120 pH, respectively. A coupling coefficient; K equal to 0.34 is achieved in the band of interest.

FIG. 9 shows the EM simulations results of the transformer inductances and the coupling coefficient. These parameters remain almost constant in the frequency range of interest. This is because the self-resonance frequency of the transformer is at higher frequency.

Simulation and Experimental Results

The wideband Balun-LNA embodiment was fabricated using 0.18 μm BiCMOS technology from Tower Jazz Semiconductor [23].

FIG. 10 shows the die micrograph of the balun-LNA embodiment, where the total area is 0.46 mm² excluding the RF and DC pads. On-wafer measurements were done using RF differential probes (G-S-G-S-G) for input and outputs. The use of RF differential input probe is necessary for calibration purposes using Cascade Microtech Impedance Standard Substrate (ISS) [24]. Although an RF differential probe is used at the input, the input signal is fed into only one port. Also, a 6-pin DC probe is used to provide the DC biasing. The balun-LNA core consumes 5 mA from 1.8V supply.

FIG. 11 shows the measured and simulated input return losses (S₁₁) for the balun-LN A. Measured S₁, is larger than 8.7 dB for the entire operating frequency range of 22-35 GHz and up to 40 GHz.

FIG. 12 displays the measured and simulated output return losses S₂₂ and S₃₃. Measured S22 is better than 9 dB from 22-29 GHz and S₃₃ is larger than 7.5 dB from 23.5-27.4 GHz. The shifting of the return loss responses at the outputs of the balun-LNA is mainly due to the variations of the small metal insulator metal (MIM) output capacitances as well as the parasitic inductances coupling to the substrate. Consequently, the measured power gains for the balun-LNA (S₂₁ and S₃₁) shift to 26.8 GHz and 27 GHz, respectively, as seen in FIG. 13, which shows S₂₁ and S₃₁ achieving a gain of 15.6 and 15.4 dB, respectively. This represents a measured differential gain boost of 2.0 dB and 2.4 dB for S₃₁ and S₂₁ compared to simulations. The measured 3-dB bandwidths for S₂₁ and S₃₁ are 7.6 GHz and 11.5 GHz, respectively. A 3.9 GHz bandwidth difference between S₂₁ and S₃₁ is mainly due to asymmetric signal path from input to outputs and unequal parasitic capacitances to the substrate.

FIG. 14 shows the measured stability of the balun-LNA embodiment in term of the stability parameter μ [25], which is derived from the measured S-parameters. The balun-LNA is unconditionally stable for both channels across the 22-35 GHz bandwidth according to μ(s)>1. The measured noise figures for both channels are shown in FIG. 15, where the noise figures between input port 1 and output port 3 (NF₃₁) and input port 1 and output port 2 (NF₂₁) vary from 4.5 dB to 5.8 dB and from 4.6 dB to 7.09 dB, respectively. NF₂₁ experiences higher noise figure particularly due to channel gain drop. In the case of a differential to single ended balun applied at the output of the proposed balun-LNA, a 3-dB differential gain increase is possible and a much lower noise figure can be achieved due to common mode noise cancellation.

The measured gain and phase imbalances are shown in FIG. 16. The gain and phase mismatches from 20-30 GHz are 1.8 dB and 12°, respectively. However, the gain mismatch can reach 5.5 dB at 35 GHz. The measurements of the 1-dB power compression points (P1dB₂₁ P1dB₃₁) and the input referred third order intercept points (IIP3₂₁ and IIP3₃₁) for both channels for the frequency range of 22-35 GHz are shown in FIG. 17.

P1dB and IIP3 higher than −14.8 and −6 dBm across 22-35 GHz are achieved for both channels, respectively. The performance of the proposed wideband balun-LNA is shown in Table I in comparison with other LNA designs operating in the same frequency spectrum. These results confirm that the balun-LNA exhibits good differential property, high power gain, low noise figure, very competitive linearity, and the lowest power consumption in the K/Ka-band of operation.

A wideband 22-35 GHz balun-LNA embodiment is implemented using −18 μm. SiGe BiCMOS technology. The balun-LNA structure implemented new linearity technique based on Gm-constant approach and utilized coupling staked transformer to improve power and noise efficiency. Analytical expressions for the wideband input matching impedance, linearity, noise figure, and stability were developed to highlight the design tradeoffs. The gain and phase mismatches for the frequency range of 20-30 GHz are 1.8 dB and 12° respectively. Power gains of 15.6 and 15.4 dB, 3-dB bandwidths of 7.6 GHz and 11.5 GHz, noise figures of 4.5-5.8 and 4.6-7.09 dB, and linearity better than −6.07 dBm are achieved between the input and two outputs. The balun-LNA consumes only 5 mA dc current from 1.8V supply and having an active area of 0.46 mm².

Noise Analysis Basis

The noise analysis presented below is based on the noise model shown in FIG. 6. Before determining the input referred voltage noise due to the base and collector shot currents of transistors Q₁, Q₂, we had to solve various circuits' impedances affected by the transformer behavior. From the noise model, Z_(x) is the impedance looking from the base of transistor Q₂ into the transformer. Similarly, Z_(c) is the impedance at the collector of Q₁. Z_(M) is the impedance due to Miller effect at transistor Q₁. Further, Z_(e), and Z_(S) are the impedances looking at the emitter and from the base into the source generator of Q1, respectively. Applying KCL analysis yields Eqs. (A1)-(A5) as follows.

$\begin{matrix} {Z_{x} \approx {Z_{2}{{}\left\lbrack {R_{{bx}\; 2} + {sL}_{b\; 2} + \frac{({Kn}){{sL}_{e\; 1}\left( {{sL}_{b\; 2} + Z_{1} + Z_{2}} \right)}\left( {{sC}_{be} + g_{m\; 1}} \right)}{{g_{m\; 1}Z_{1}} - {({Kn}){{sL}_{e\; 1}\left( {{sC}_{be} + g_{m\; 1}} \right)}}} + Z_{1}} \right\rbrack}}} & ({A1}) \end{matrix}$

where Z₁, Z₂ are defined earlier.

$\begin{matrix} {Z_{c} \approx {Z_{1}{{}\left\lbrack {{sL}_{b\; 2} + \frac{({Kn}){{sL}_{e\; 1}\left( {{sL}_{b\; 2} + Z_{1} + Z_{2}} \right)}\left( {{sC}_{be} + g_{m\; 1}} \right)}{{g_{m\; 1}Z_{1}} - {({Kn}){{sL}_{e\; 1}\left( {{sC}_{be} + g_{m\; 1}} \right)}}} + Z_{2}} \right\rbrack}}} & ({A2}) \\ {{Z_{\mu} \approx {\left\lbrack Z_{c} \right\rbrack + \left( \frac{1}{{sC}_{bc}} \right)}}{Z_{M} \approx \left( \frac{Z_{\mu}}{\left( {1 - A_{v}} \right)} \right)}} & ({A3}) \end{matrix}$

Where A_(v) is the voltage gain of the balun-LNA.

$\begin{matrix} {Z_{e} \approx {{sL}_{e\; 1}\left\lbrack {1 + \frac{({Kn})\left( {{g_{m\; 1}Z_{1}} - {({Kn}){{sL}_{e\; 1}\left( {{sC}_{be} + g_{m\; 1}} \right)}}} \right)}{\left( {{sL}_{b\; 2} + Z_{z} + Z_{2}} \right)\left( {{sC}_{be} + g_{m\; 1}} \right)}} \right\rbrack}} & ({A4}) \\ {{Z_{s} \approx}\left( {R_{bx} + R_{L_{b}} + {sL}_{b} + \left( \frac{R_{s}}{{{sC}_{pad}R_{s}} + 1} \right)} \right)} & ({A5}) \end{matrix}$

The base and collector current shot noises for transistors Q₁, Q₂ are given by:

i ² _(n,b1,2) =2qI _(B1,2)  (A6)

i ² _(n,c1,2) =2qI _(C1,2)  (A7)

where q is the electron charge constant, and I_(B1,2) and I_(C1,2) are the collector and base currents for transistors Q₁, Q₂, respectively.

The input referred voltage noise due to the base and collector currents shot noises of transistors Q₁ and Q₂ including the parasitic base resistance R_(bx2) are shown in (A8)-(A12) where β is the current gain of Q₁ and Q₂.

$\begin{matrix} {\frac{\overset{\_}{v_{{ni},{Q\; 1}}^{2}}}{\overset{\_}{i_{n,{c\; 1}}^{2}}} \approx {{\left\lbrack {1 - \frac{Z_{e}}{Z_{e} + {\left( \frac{r_{e}}{{{sC}_{be}r_{e}} + 1} \right)\left( \frac{1}{B} \right)\left( \frac{Z_{M}Z_{s}}{Z_{M} + Z_{s}} \right)}}} \right\rbrack \frac{1}{g_{m\; 1}}}}^{2}} & ({A8}) \\ {\frac{\overset{\_}{v_{{ni},{Q\; 1}}^{2}}}{\overset{\_}{i_{n,{b\; 1}}^{2}}} \approx {\begin{matrix} {{\left( \frac{Z_{M}Z_{s}}{Z_{M} + Z_{s}} \right){}\left( {\left( \frac{\beta \; r_{e}}{{{sC}_{be}\beta \; r_{e}} + 1} \right) + {\beta \; Z_{e}}} \right)} +} \\ {\frac{Z_{e}}{Z_{e} + \left( \frac{r_{e}}{{{sC}_{be}\; r_{e}} + 1} \right) + {\left( \frac{1}{\beta} \right)\left( \left( \frac{Z_{M}Z_{s}}{Z_{M} + Z_{s}} \right) \right)}}\frac{1}{g_{m\; 1}}} \end{matrix}}^{2}} & ({A9}) \\ {\frac{\overset{\_}{v_{{ni},{Q\; 2}}^{2}}}{\overset{\_}{R_{{bx}\; 2}^{2}}} \approx {{\left\lbrack \frac{Z_{2}}{Z_{2} + Z_{x}} \right\rbrack\left\lbrack \frac{1}{\left( {\frac{g_{m\; 1}}{g_{m\; 3}} + {nK}} \right)} \right\rbrack}}^{2}} & ({A10}) \\ {{\frac{\overset{\_}{v_{{ni},{Q\; 2}}^{2}}}{\overset{\_}{i_{n,{b\; 2}}^{2}}}\quad} \approx {{\left\lbrack {\left( \frac{Z_{2}Z_{x}}{Z_{2} + Z_{s}} \right) + \frac{\left( {{R\text{?}} + {sL}_{e\; 2}} \right)}{\begin{matrix} {\left( {{R\text{?}} + {sL}_{e\; 2}} \right) + \left( \frac{r_{e\; 2}}{{{sC}_{{be}\; 2}r_{e\; 2}} + 1} \right) +} \\ {\left( \frac{1}{\beta} \right)\left( \frac{Z_{x}}{{{sC}_{p\; 2}Z_{x}} + 1} \right)} \end{matrix}}} \right\rbrack {\quad{\quad\left\lbrack \frac{1}{\frac{g_{m\; 1}}{g_{m\; 3}} + {nK}} \right\rbrack }^{2}}}}} & ({A11}) \\ {\frac{\overset{\_}{v_{{ni},{Q\; 2}}^{2}}}{\overset{\_}{i_{n,{e\; 2}}^{2}}} \approx {{\left\lbrack {1 - \left\lbrack \frac{R\text{?}}{\begin{matrix} {\left( {{R\text{?}} + {sL}_{e\; 2} + \left( \frac{r_{e\; 2}}{{{sC}_{{be}\; 2}r_{e\; 2}} + 1} \right)} \right) +} \\ {\left( \frac{1}{\beta} \right)\left( \frac{\left( {R_{{bx}\; 2} + Z_{x}} \right)}{{{sC}_{p\; 2}\left( {R_{{bx}\; 2} + Z_{x}} \right)} + 1} \right)} \end{matrix}} \right\rbrack} \right\rbrack \cdot {\quad\left\lbrack \frac{1}{\frac{g_{m\; 1}}{g_{m\; 3}} + {nK}} \right\rbrack }_{2}}}} & ({A12}) \\ {{\text{?}\text{indicates text missing or illegible when filed}}\mspace{265mu}} & \; \end{matrix}$

Now, taking the outcomes from (A8)-(A12) and normalize it to the source generator impedance R_(S) results in (A13)-(A17). ψ₁(ω)−ψ₅(ω) is the total equivalent input referred voltage noise power shown in (14).

$\begin{matrix} {{\Psi_{1}(\omega)} \approx {\frac{1}{2R_{s}}{\left\lbrack {1 - \frac{Z_{e}}{Z_{e} + \left( \frac{r_{e}}{{{sC}_{be}r_{e}} + 1} \right) + {\left( \frac{1}{\beta} \right)\left( \frac{Z_{M}Z_{s}}{Z_{M} + Z_{s}} \right)}}} \right\rbrack }^{2}}} & ({A13}) \\ {{\Psi_{2}(\omega)} \approx {\frac{1}{2\beta \; R_{s}}{\begin{matrix} {{\left( \frac{Z_{M}Z_{s}}{Z_{M} + Z_{s}} \right){} \left( {\left( \frac{\beta \; r_{e}}{{{sC}_{be}\beta \; r_{e}} + 1} \right) + \left. \quad{\beta \; Z_{e}} \right)} \right)} +} \\ \frac{Z_{e}}{Z_{e} + \left( \frac{r_{e}}{{{sC}_{be}r_{e}} + 1} \right) + {\left( \frac{1}{\beta} \right)\left( \left( \frac{Z_{M}Z_{s}}{Z_{M} + Z_{s}} \right) \right)}} \end{matrix}}^{2}}} & ({A14}) \\ {{\Psi_{3}(\omega)} \approx \frac{R_{{bx}\; 2}{\left\lbrack \frac{Z_{2}}{Z_{2} + Z_{x}} \right\rbrack }^{2}}{R_{s}}} & ({A15}) \\ {{\Psi_{4}(\omega)} \approx {\frac{1}{2\beta^{2}R_{s}}{\left\lbrack {\left( \frac{Z_{2}Z_{x}}{Z_{2} + Z_{x}} \right) + \frac{\left( {{R\text{?}} + {sL}_{e\; 2}} \right)}{\left( {{R\text{?}} + {sL}_{e\; 2}} \right) + \left( \frac{r_{e\; 2}}{{{sC}_{{be}\; 2}r_{e\; 2}} + 1} \right) + {\left( \frac{1}{\beta} \right)\left( \frac{Z_{x}}{{{sC}_{p\; 2}Z_{x}} + 1} \right)}}} \right\rbrack }^{2}}} & ({A16}) \\ {{\Psi_{5}(\omega)} \approx {\frac{1}{2\beta^{2}R_{s}}{\left\lbrack {1 - \left\lbrack \frac{{R\text{?}} + {sL}_{e\; 2}}{\begin{matrix} {\left( {{R\text{?}} + {sL}_{e\; 2} + \left( \frac{r_{e\; 2}}{{{sC}_{{br}\; 2}r_{e\; 2}} + 1} \right)} \right) +} \\ {\left( \frac{1}{\beta} \right)\left( \frac{\left( {R_{{bx}\; 2} + Z_{3}} \right)}{{{sC}_{p\; 2}\left( {R_{{bx}\; 2} + Z_{2}} \right)} + 1} \right)} \end{matrix}} \right\rbrack} \right\rbrack }^{2}}} & ({A17}) \\ {{\text{?}\text{indicates text missing or illegible when filed}}\mspace{281mu}} & \; \end{matrix}$

Further Embodiments

With the ever growing consumers' demands for high data rate wireless communications, bandwidth, and radar sensor devices are the main surge in the semiconductor market industry. Due to overcrowding on the lower frequency spectrum, the Federal Communications Commission (FCC) has standardized unlicensed microwave and millimeter-wave frequencies to serve the need [26]-[27]. To improve spectrum efficiency, the FCC authorizes the ultra-wideband devices (UWB) to operate concurrently in coexistence with radio astronomy from 23.6-24 GHz, industrial-scientific-medical (ISM) from 24.05-24.25 GHz, IEEE 802.16 standard for wireless metropolitan area network (WiMAN) ranging from 10-66 GHz, short-range and long-range vehicular radar sensors for collision avoidance from 22-29 GHz and from 77-81 GHz, and military radar sensor for unmanned aerial vehicle (UAV) at 35-37 GHz [3]. This frequency spectrum allocation dilemma stems from the fact that these UWB devices operate not only in coexistence with already standardized adjacent bands, but it overlaps them. For that reason, the FCC regulates the effective isotropic radiated power (EIRP) for the UWB devices to limit the interferences on the spectrum [26]-[27]. Transceivers targeting microwave and mm-wave applications are reported with limited agility using single-band approach [29]-[37], dual-band design [38]-[39], and lastly wideband RF front-end receivers [40]-[42].

Dedicated transceivers aiming for microwave and mm-wave specific applications have come to light in recent years. A 0.18-μm 24 GHz CMOS RF front end was reported in [29]. An automotive short-range and long-range radar sensor for Ka- and W-bands application with its FCC regulations was addressed in [30]-[31]. Various broadband architectural transceivers designs for the 60 GHz wireless communications are reported in [32]-[34]. Such receivers with single-balanced RF mixers tend to suffer from local oscillator (LO) leakage, thus causing receiver desensitization. Fully integrated using 4 and 8 elements phased array receivers in CMOS for 24 GHz ISM band are reported in [35]-[16]. Further, a fully integrated 77 GHz BiCMOS phased array receiver with dipole antenna on chip for long-range automotive radar sensor is reported in [37].

To increase versatility and functionality, dual-band transceivers/receivers are demonstrated in [38]-[39]. Adding more passive components to achieve dual-bands resonance introduces high signal loss and increases chip area; hence, increases the power consumption. The dual-bands 24/31 GHz based sub-harmonic receiver architecture in [38] requires fine tuning for the quadrature phases generation schemes as well for amplitude mismatches to improve bands rejection. An automotive dual-bands direct conversion transceiver for collision avoidance is reported in [39]. The large frequency spread of the transceiver frequency planning causes two dedicated local oscillators running at 22 and 77 GHz to be integrated on chip. The drawback is more power consumption, larger chip area, and more complex layout floor planning not to mention the phase noise issues. As we can see; single-band or dual-bands transceivers have limited flexibility. More desired approach targets multi-standards multi-bands using wideband RF front-end transceivers to increase functionality suffers from limited linearity [40]-[42].

A further embodiment for a wideband direct conversion current mode receiver for concurrently coexistent multi-standards multi-bands mm-wave applications is discussed. The receiver consists of a main path correlating the down converted output current gain stages into low input impedance of a trans-impedance amplifier (TIA) with a built-in feed-forward high-pass anti-aliasing blockers filter; no RF voltage gain. In addition, the auxiliary path utilizes an attenuator first block providing robustness to high power jamming UAV radar signals from 35-37 GHz. The architectural receiver design concept is similar to [43]-[48] where current mode gain is maintained throughout the receiver RF front-end. However, passive mixer increases the noise figure of the receiver chain, thus a second gain stage is needed. A class AB amplifier with low input impedance is added without limiting the receiver linearity. Consequently, the class AB amplifier gain stage immunes the receiver from I/Q interaction due to passive mixer 50% duty cycle [50]. The direct conversion receiver is targeted to down convert all IEEE standards within 22-44 GHz spectrum with 500 MHz baseband frequency (IF) bandwidth supporting UWB device applications. The wideband power local oscillator (LO) is provided from; R&S ZVA 67 GHz; vector network analyzer (VNA) with quad power sources and very acceptable phase noise.

Receiver Architecture Using the Low Noise Amplifier

A wideband versatile multi-standards multi-bands direct conversion receiver chain for microwave and mm-wave coexistent applications 22-44 GHz is shown in FIG. 18 using 0.18-μm BiCMOS technology.

The receiver architecture consists of a main path; and an auxiliary one dedicated to high power jamming blocker for military unmanned aerial vehicle (UAV) radar application 35-37 GHz. The latter one is designed to have an attenuator first block with linear phase characteristics. A receiver signal strength indicator block (RSSI) senses the incoming antenna signal power level and controls path selectivity. The main path consists of a wideband active balun-LNA reported in [49] followed by a low input impedance class AB amplifier.

The differential current mode outputs of the two successive gain stages are down-converted by an ac coupled doubly-balanced passive mixers through the correlation of differential In-phase/quadrature signals using quadrature all pass filter (QAP) design fed externally from a differential local oscillator (LO). The cross-correlated current output is converted to voltage using a feed-forward trans-impedance amplifier (TIA) with low input impedance. Furthermore; a feed-forward high-pass polyphase filter provides cancellation mechanism at the output TIA node and immune the receiver from out of band interferers (OBI), blockers, and reduce the effect of in-band aliasing. Note that the noise contribution of this high-pass polyphase cancellation filter is minimal owing to its low gain frequency response in band. This design method increases receiver flexibility and functionality and reduces its dependency on external duplexers and bulky MEMS filter as in [38]. Hence, the bill of materials (BOM) is reduced. The proponents of the proposed receiver architecture including both paths are as follows:

-   -   1) Utilizing current mode amplification in the RF front-end, no         RF voltage gain. Thus, low noise figure (NF) and high in-band         linearity for the RF front-end is maintained.     -   2) Class AB amplifier with low input impedance preceded by a         highly linear balun-LNA bolsters the current amplification mode         without degrading the linearity compared to [43]; [45]; where         regular common source transconductance gm stages are used.     -   3) Having successive low input impedance throughout the         multi-gain stages of the RF front-end helps preserve the         wideband operation across the frequency band of interest, and         leads to less distortion in the mixer and the nonlinear output         impedances of the multi-gain current mode blocks. Hence, the         OBIs' experience no voltage gain amplifications and the first         voltage gain happens only at baseband after the low pass filter,         which provides channel filtering selectivity to mitigate the         OBI.     -   4) Having an active wideband single to differential balun-LNA         with asymmetric paths from input to outputs can causes amplitude         and phase mismatches due to unequal parasitics between the two         paths. To resolve this dilemma; single to differential passive         transformer is being used as part of the matching network for a         fully differential LNA [47]-[48].

However, a large insertion loss (<−4 dB) due to passive transformer is inevitable and technology dependent. Thus, the noise figure is degraded. The alternative approach is placing a differential class AB gain stage after the balun-LNA to improve the common mode rejection and cancel any mismatches without linearity limitation. Furthermore; the class AB amplifier has built in amplitude and phase mismatches cancellation scheme. The architectural design advantages for this mm-wave receiver are ubiquitous. A more detailed analysis of these benefits is presented below on the circuit implementation level.

Balun-LNA

A single to differential highly linear active wideband balun-LNA is designed to amplify the 22-44 GHz frequency spectrum. The architecture of the active balun-LNA has a wideband input matching network consisting of base inductance; L_(b); ac coupled transformer between L_(e1) and L_(b2), and coupling parasitic capacitances to the substrate as losses. The input matching response behavior is dependent on the coupling coefficient; K; and the turn ratios between the transformer windings. A resonant frequency shift is adjusted with the base inductance L_(b). A wideband performance is maintained due to low quality factor of the matching network through its poles and zeros cancellations. Yet, each inductor must have a high quality factor with high self resonance to keep the noise figure low. The output matching network consists of inductive peaking capacitively coupled to the class AB amplifier with low input impedance.

The balun-LNA architecture consists of two paths as follows; a main transconductance gm gain stage path coupled to an auxiliary one using a transformer. The benefits of adding this transformer translates into an increase in the signal to noise ratio (SNR) at the base-emitter junction of the auxiliary path. Hence, a gain boost for less static dc power is achieved. Further; a lower input referred noise is seen in the auxiliary path due to the transformer benefits. The 3-dB differential power gain S₂₁ is 15 dB and the bandwidth is limited by the return loss S₁₁<−10 dB across the entire frequency band of interest. A linearity improvement technique is based on a constant G_(m)-cell transconductance behavior for the balun-LNA structure. The constant G_(m)-cell transconductance is established through equal emitters' area (A_(e)) ratios and proper base-emitter junction biasing. The constant small signal G_(m)-cell transconductance remains independent of input and output variations under large signal behavior. The proposed structure achieves a second order intermodulation (IM₂) cancellation, and the measured input referred third order intermodulation (IIP₃) and differential NF are >−1 dB_(m) and <3.5 dB; respectively. The gain and phase mismatches are kept to a minimum. The total power consumption is less than 18 mW drawn from a 1.8V power supply.

Class AB Amplifier

The class AB amplifier is preceded with a highly linear current mode balun-LNA. Note that to maintain receiver chain linearity and suppress the passive mixer noise contribution; a highly linear second gain stage amplifier is required. Current mode operation in RF front-end entails numerous benefits from noise to linearity; no RF voltage gain [43]-[45]; [47]-[48]. To keep the voltage swing to a minimum at the input of the class AB amplifier; a low differential input impedance has to be maintained across the bandwidth of interest. The input impedance consists of the parallel combination of two sections. The first part is made of the diode connected bipolar device Q_(2A) junction in series with inductor; L₂. The second part consists of the common base device Q_(1A) in series with inductor; L₁. The derived input impedance of the class AB amplifier is based on the small signal model.

Equation (1) shows the derived input impedance below;

$\begin{matrix} {{Z_{{in},{AB}}(s)} = {{jwL} + \frac{V_{T}}{I_{C} + {V_{T}{sC}_{be}}}}} & (1) \end{matrix}$

where we have the assumption I_(C1)=I_(C2)=I_(C), L₁=L₂=L, and V_(T) is the thermal voltage. We also assumed the devices Q_(1A) and Q_(2A) emitter’ area sizes are equal.

Further, the class AB amplifier architecture has a built-in cancellation mechanism for all phases and amplitudes mismatches generated from the asymmetry balun-LNA structure. Although the differential outputs of the balun-LNA are evenly loaded, the input signal asymmetry path to the outputs causes unequal coupling parasitic to the substrate, thus the phase and amplitude mismatches. To resolve this dilemma, the class AB amplifier on a single sided output consists of in-phase input current buffer combined with an out of phase current shifted (180°+α) to average the phase mismatches generated from the balun-LNA and the class AB amplifier. Once measuring the differential signal at the outputs of the class AB amplifier, a complete phase error cancellation is possible in theory. However, the amplitude mismatch error is limited by the class AB amplifier output currents ratios. This partial amplitude error cancellation can limit the phase error cancellation mechanism. Note that the phase and amplitude cancellation mechanism is independent of any passive components and only limited by the active devices mismatches, thus the operation for the error cancellation mechanism is frequency independent and can reach well into the millimeter-wave frequencies. Simulations show phase and amplitude mismatches less than 1.7° and less than 0.5 dB, respectively across 0-45 GHz frequency band.

Passive Mixer and I/Q Generator

We use a simple model of the millimeter-wave direct conversion I/Q receiver front-end using ac coupled fully balanced current-driven quadrature passive mixers with 50% duty cycles. The 2 stages balun-LNA is a transconductor that supplies the RF current modeled by a current source and having load impedance Z_(L)(s). The second transconductance gain stage is a class AB amplifier with low differential input impedance, thus no RF voltage gain and the receiver linearity is maintained. In addition, the proponents of the ac coupled second gain stage class AB amplifier to the passive mixers are not only limited to the second order intermodulation product improvement, but also help eliminate the I/Q channels crosstalk or interaction due to the lack of reverse isolation between RF and baseband side of the passive mixer. This phenomenon is based on baseband voltage offset produced at the input current buffer impedance; where an antiphase current image is generated from one set of switches to another cause I/Q interaction that affect high and low sides mismatches of gain conversion, linearity (IIP2, IIP3), and noise figure of the current buffer [50]. Then, the major problem with using 50% duty cycle approach has been resolved due to the second class AB gain stage without sacrificing linearity. Furthermore, no dc current is commutating in the deeply trenched dual-well nMOS switches, thus the 1/f noise is greatly reduced at the input current buffer.

The designer has control over the device's size and the LO characteristics. In the passive mixer increasing the device's size width helps reduce the switch on resistance, thus its thermal noise contribution is lower. The dc biasing condition at the drain and source of the CMOS switch is set from the input current buffer impedance. Consequently, the dc bias voltage level of the LO signal is a paramount factor in controlling the switches mode of operation. The characteristics of the LO driver affects the performance of the mixer.

Therefore, a large LO signal can help improve the passive mixer conversion gain as well its noise figure. In a 50% duty cycle fully balanced passive mixer, the gain conversion is ideally equal to 2/π. However, if the switches of the quadrature passive mixer experience less turn on time than off time then the conversion gain as well as the noise figure are improved at the expense of less linearity.

An in-phase/quadrature phase generator is placed in the LO signal path due to relatively high insertion loss. Alternatively, the QAP can be placed the RF signal path however, the tradeoffs between gain and noise figure are to be considered. The simulations results for QAP in the frequency range 22-44 GHz show an insertion loss of 13 dB with in-phase/quadrature amplitude and phase mismatches less than 1.8 dB and ±3°, respectively. The tradeoff is between keeping low insertion loss versus maintaining flat phase response. The total LO power requirement for the passive mixer is 15 dBm using a switch on resistance of 40Ω. From the combination of the LO power signal and the switches sizes, the quadrature passive mixer reaches an acceptable 4 dB noise figure with no power consumption.

TIA with Out of Band Interferes Rejection Filter

A feed-forward trans-impedance amplifier (TIA) also known as open loop TIA is deployed to convert the down converted correlated output current from the in-phase/quadrature passive mixers into voltages at the differential outputs of the TIA. Furthermore, an auxiliary path uses a feed-forward high pass polyphase filter (HPF) to reject blockers and LO harmonics leakage due to direct conversion receiver architecture. Note the importance of 3^(rd) and 5^(th) LO harmonics rejection that cause intermodulation with blockers and interferes to down convert to UWB baseband. Also, a buffer for dc interface is implemented to isolate between the TIA input impedance and the active HPF with no phase and amplitude changes. C_(L), C_(in) are designated as the total load and total input capacitances, respectively. The trans-impedance transfer function is defined as:

$\begin{matrix} {{Z_{T}(s)} = {\frac{R_{T}}{\left( {1 + {s/\omega_{p\; 1}}} \right)\left( {1 + {s/\omega_{p\; 2}}} \right)} \cdot \left\lbrack \left( {1 - {\left( \frac{s/\omega_{p\; 3}}{{s/\omega_{p\; 3}} + 1} \right)\left( \frac{{sgm}_{2}C_{s}}{{sC}_{s} + {gm}_{2}} \right)}} \right) \right\rbrack}} & (2) \end{matrix}$

where R_(T) is defined as the output impedance of the TIA. Poles ω_(p1)=gm₁/C_(in) and ω_(p2)=1/Z_(T)C_(L) are designated as the dominant and non-dominant poles for the feed-forward TIA, respectively.

For the open loop TIA and the feed-forward auxiliary cancellation path transconductances, gm₁ and gm₂ are set equals. The active HPF is preceded by a coarse first order non-evasive HPF with ω_(p3)=1/C_(dec)R_(bias). The active HPF is established using a capacitively degenerated common source stage. A fourth order HPF is seen at the differential output of the feed-forward TIA. Higher order of the feed-forward cancellation filter can be easily implemented through multi-cascaded HPF stages at the expense of greater in-band noise figure. Note that in the case of desirable reconfigurable bandwidth to support various IEEE standards, the degenerated capacitance at the HPF is bit controlled through an encoder to change its poles and zeros' location so as to maintain the same attenuation factor. Furthermore, the output impedance of the TIA has to incorporate a parallel conductance with variable bias control as to trade the trans-impedance gain for the bandwidth. From simulation results, the trans-impedance gain is 55 dBΩ with 500 MHz bandwidth with no stability issues in accordance with minimum UWB requirements. In addition, the open loop TIA achieves 20 dB attenuations of the third harmonic tone at 1.5 GHz. The total system power consumption is 18.6 mA drawn from a 1.8V supply.

When used in this specification and claims, the terms “comprises” and “comprising” and variations thereof mean that the specified features, steps or integers are included. The terms are not to be interpreted to exclude the presence of other features, steps or components.

The features disclosed in the foregoing description, or the following claims, or the accompanying drawings, expressed in their specific forms or in terms of a means for performing the disclosed function, or a method or process for attaining the disclosed result, as appropriate, may, separately, or in any combination of such features, be utilised for realising the invention in diverse forms thereof.

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1. An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor; a second transistor; and a third transistor, wherein: the first, second and third transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement.
 2. The amplifier of claim 1, wherein the transconductance cell is configured with a collector terminal of the first transistor coupled to a base terminal of the second transistor and an emitter terminal of the third transistor.
 3. The amplifier of claim 1, further comprising: a first inductor coupled to an emitter of the first transistor; a second inductor coupled between a collector of the first transistor and a base of the second transistor, wherein the first inductor and the second inductor are arranged to operate respectively as a first coil of a transformer and a second coil of a transformer.
 4. The amplifier of claim 3, wherein the transformer is configured to perform at least one of increasing the voltage gain of the amplifier and/or increasing the signal bandwidth of the amplifier.
 5. The amplifier of claim 4, wherein the signal input arrangement comprises an impedance matching circuit which is coupled to the first transistor, the impedance matching circuit comprising the first inductor and a third inductor each coupled to a base of the first transistor.
 6. The amplifier of claim 1, further comprising: a fourth inductor coupled between an emitter of the third transistor and a collector of the first transistor.
 7. The amplifier of claim 1, wherein the collector of the second transistor is coupled to the emitter of a fourth transistor, and wherein the first, second, third and fourth transistors are arranged in a common-emitter configuration.
 8. The amplifier of claim 1, wherein a base of the third transistor, a base of the fourth transistor and a power supply input are coupled to one another.
 9. The amplifier of claim 8, wherein the signal output arrangement comprises: a first output portion coupled to a collector of the third transistor; and a second output portion coupled to a collector of the fourth transistor.
 10. The amplifier of claim 9, wherein the first output portion includes a first pair of series connected inductors and a first output terminal coupled to the connection between the first pair of inductors, and wherein the second output portion includes a second pair of series connected inductors and a second output terminal coupled to the connection between the second pair of inductors.
 11. The amplifier of claim 10, further comprising: a first resistor coupled between the first output portion and the power supply input; and a second resistor coupled between the second output portion and the power supply input.
 12. The amplifier of claim 10, wherein the inductance of the first pair of inductors is equal to the inductance of the second pair of inductors.
 13. The amplifier of claim 11 is configured to be operable with a passive mixer and a trans-impedance amplifier and the signal output arrangement is coupled to a class AB amplifier.
 14. The amplifier of claim 1, wherein the first signal comprises at least one signal having a frequency of 22 GHz to 35 GHz.
 15. The amplifier of claim 1, wherein the amplifier is constructed using a SiGe BiCMOS process.
 16. A method of operating an amplifier including a signal input arrangement, a signal output arrangement, a first transistor, a second transistor, and a third transistor, the method comprising: receiving, by a transconductance cell, a first signal from the signal input arrangement; amplifying the first signal; and outputting an amplified first signal to the signal output arrangement, wherein the first, second and third transistors are coupled to one another to form the transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement.
 17. A receiver incorporating an amplifier, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor; a second transistor; and a third transistor, wherein: the first, second and third transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. 